Collaborative voltage scaling with online STA and variable-latency datapath

Authors:
Tay-Jyi Lin;Pi-Cheng Hsiao;Chi-Hung Lin;Shu-Chang Kuo;Chou-Kun Lin;Yu-Ting Kuo;Chih-Wei Liu;Yuan-Hua Chu
Affiliations:
Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan Roc;Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan Roc;Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan Roc;Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan Roc;Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan Roc;National Chiao Tung University, Hsinchu, Taiwan Roc;National Chiao Tung University, Hsinchu, Taiwan Roc;Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan Roc
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

This paper presents an event-driven adaptive voltage scaling (AVS) system, where a vanguard collaborates with a rearguard to find a minimal supply voltage. While the vanguard is responsible for the slack cycle time estimation, the rearguard allows voltage over-scaling with a variable-latency datapath. An improved vanguard is proposed based on online static timing analysis (STA), which monitors a scalable number of critical path candidates at run time. In our simulations, the delay estimation error is within 10%, which is relatively small compared to critical path variations of prevailing multi-Vt designs in deep-submicron era. A testchip with a 32-bit tiny RISC has been fabricated with the TSMC 65nm LP process technology to demonstrate the effectiveness.