Data driven signal processing: an approach for energy efficient computing
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Error Analysis for the Support of Robust Voltage Scaling
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Using adaptive routing to compensate for performance heterogeneity
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Collaborative voltage scaling with online STA and variable-latency datapath
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Conventional voltage scaling techniques rely on the characterization and monitoring of a unique critical path. However, the uniqueness of the critical path is a difficult requirement to establish in modern VLSI technologies due to the growing impact of process variations and interconnect parasitics on delay. This paper presents an on-chip critical path emulator architecture which tracks the changing critical path. The ability to emulate the actual critical path recovers most of the large margin added by conventional systems to guarantee a robust operation at all conditions. Due to the reduced margin, the proposed architecture is up to 45% and 21% more energy efficient compared to conventional open-loop and closed-loop voltage scaling systems respectively.