VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Adaptive channel queue routing on k-ary n-cubes
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
Efficient adaptive voltage scaling system through on-chip critical path emulation
Proceedings of the 2004 international symposium on Low power electronics and design
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive Power Management for the On-Chip Communication Network
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Quantified Impacts of Guardband Reduction on Design Process Outcomes
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Process variation-aware routing in NoC based multicores
Proceedings of the 48th Design Automation Conference
Computers and Electrical Engineering
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
| Hi-index | 0.00 |
Scalable and power efficient multi-core architectures must be performance heterogeneous to accommodate semi-conductor parametric variations and non-uniform access to shared resources. Due to its rate matching, a NoC on a Voltage-Frequency Island architecture can connect cores without forcing each one to give up its own operating point for the chip-wide common worst case. With run-time adaptive routing and task-to-core mapping, a NoC can run at the average not the worst case network saturation bandwidth. These run-time processes compensate for variations because they match application resource requirements with heterogeneous cores and routers. We focus on adaptive routing that simultaneously combats communication load imbalance from on-die variations and application topology. We show that even with static, fixed task-to-core mapping on multi-core architectures affected by stochastic variations, our MATC router increases the expected saturation bandwidth by 7–25% vs Dimension Order router. With systematic variations, the improvements are 5–50%. These gains compensate for saturation bandwidth degradation due to manufacturing variations and help to reduce design guard-bands.