Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels

Authors:
Chen-Ling Chou;U. Y. Ogras;R. Marculescu
Affiliations:
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2008

Citing 0
Cited 25

Using adaptive routing to compensate for performance heterogeneity

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs

Proceedings of the 7th ACM international conference on Computing frontiers
Communication-aware task assignment algorithm for MPSoC using shared memory

Journal of Systems Architecture: the EUROMICRO Journal
Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Virtual point-to-point connections for NoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Convex-based DOR routing for virtualization of NoC

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks

Microprocessors & Microsystems
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Dynamic decentralized mapping of tree-structured applications on NoC architectures

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip

Proceedings of the 38th annual international symposium on Computer architecture
A latency simulator for many-core systems

Proceedings of the 44th Annual Simulation Symposium
Power-aware run-time incremental mapping for 3-D networks-on-chip

NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
Application-aware deadlock-free oblivious routing based on extended turn-model

Proceedings of the International Conference on Computer-Aided Design
A3MAP: Architecture-aware analytic mapping for networks-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

Integration, the VLSI Journal
A survey on application mapping strategies for Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
Reliable energy-aware application mapping and voltage-frequency island partitioning for GALS-based NoC

Journal of Computer and System Sciences
Mapping on multi/many-core systems: survey of current and emerging trends

Proceedings of the 50th Annual Design Automation Conference
Smart hill climbing for agile dynamic mapping in many-core systems

Proceedings of the 50th Annual Design Automation Conference
CusNoC: fast full-chip custom NoC generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Virtual networks -- distributed communication resource management

ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Design for test and reliability in ultimate CMOS

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Efficient multicast schemes for 3-D Networks-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal
Energy and buffer aware application mapping for networks-on-chip with self similar traffic

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.03

Visualization

Abstract

Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known a priori. This paper targets real-time applications which are dynamically mapped onto embedded MPSoCs, where communication happens via the Network-on-Chip (NoC) approach, and resources connected to the NoC have multiple voltage levels. We address precisely the energy- and performance-aware incremental mapping problem for NoCs with multiple voltage levels and propose an efficient technique (consisting of region selection and node allocation) to solve it. Moreover, the proposed technique allows for new applications to be added to the system with minimal in- terprocessor communication overhead. Experimental results show that the proposed technique is very fast, and as much as 50% communication energy savings can be achieved compared to using an arbitrary allocation scheme.