Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Terrestrial cosmic ray intensities
IBM Journal of Research and Development
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Critical power slope: understanding the runtime effects of frequency scaling
ICS '02 Proceedings of the 16th international conference on Supercomputing
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The Soft Error Problem: An Architectural Perspective
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Variability and energy awareness: a microarchitecture-level perspective
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
The effects of energy management on reliability in real-time embedded systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Energy-efficient server clusters
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Soft errors issues in low-power caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Reliable energy-aware application mapping, task scheduling, and voltage-frequency island partitioning so as to minimize the energy consumption while preserving the required bandwidth and latency is considered as a challenging problem in the designing of Multi-Processor System-on-Chip. To achieve modular design and low power consumption, Globally Asynchronous Locally Synchronous (GALS) design paradigm is a promising approach which fits very well with the voltage-frequency islands concept. In this paper, we formulate mapping problem of a real-time application with stochastic execution times onto multicore systems, scheduling tasks on processors, and assigning voltage-frequency levels to Processing Elements (PEs) as a Mixed Integer Linear Programming (MILP) in GALS-based Network-on-Chip. Furthermore, owing to the importance of reliability issue, we address the effects of transient faults in our proposed MILP formulation such that the reliability of the whole system incorporating several heterogeneous PEs is guaranteed to be better than a given threshold. Due to the NP-hardness of such a problem, a rounding by sampling-based heuristic algorithm is provided. Experimental results based on E3S benchmark suite and some real applications show the effectiveness of our proposed heuristic in achieving a near-optimal solution in a small fractional of time needed to find the optimal solution. Experimental results also show that, our formulation preserves the required reliability and increases the energy consumption by 70% in some cases.