The turn model for adaptive routing
Journal of the ACM (JACM)
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 46th Annual Design Automation Conference
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Microelectronics Journal
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
Integration, the VLSI Journal
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Journal of Computer and System Sciences
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient VFI (Voltage-Frequency Island) based Network-on-Chip. Unlike the recent work [10] which only performs partitioning together with voltage-frequency assignment for a given mesh network layout, our framework consists of three key VFI-aware components, i.e., VFI-aware partitioning, VFI-aware mapping, and VFI-aware routing. Thus our technique effectively reduces VFI overheads such as mixed clock FIFOs and voltage level converters by over 82% and energy consumption by over 9% compared with the previous state-of-art works [10].