A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Power Aware Design Methodologies
Power Aware Design Methodologies
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SEAS: a system for early analysis of SoCs
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
Methods for power optimization in distributed embedded systems with real-time requirements
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Post-placement voltage island generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Proceedings of the conference on Design, automation and test in Europe
Temperature and voltage aware timing analysis: application to voltage drops
Proceedings of the conference on Design, automation and test in Europe
Energy-aware synthesis of networks-on-chip implemented with voltage islands
Proceedings of the 44th annual Design Automation Conference
A provably good approximation algorithm for power optimization using multiple supply voltages
Proceedings of the 44th annual Design Automation Conference
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Voltage island-driven floorplanning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Proceedings of the 2008 international symposium on Physical design
Postplacement voltage assignment under performance constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
Proceedings of the 2009 international symposium on Physical design
Multi-voltage floorplan design with optimal voltage assignment
Proceedings of the 2009 international symposium on Physical design
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Voltage-island driven floorplanning considering level-shifter positions
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 ACM Symposium on Applied Computing
Panoptic DVS: a fine-grained dynamic voltage scaling framework for energy scalable CMOS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Power efficient voltage islanding for Systems-on-Chip from a floorplanning perspective
Proceedings of the Conference on Design, Automation and Test in Europe
Power aware SID-based simulator for embedded multicore DSP subsystems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-Aware Loop Parallelism Maximization for Multi-core DSP Architectures
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Floorplanning considering IR drop in multiple supply voltages island designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Postplacement Voltage Island Generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Static noise margin analysis of sub-threshold SRAM cells in deep sub-micron technology
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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Voltage islands enable core-level power optimization for System-on-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves island partition creation, voltage level assignment and floorplanning. The task of island partition creation and level assignment have to be done simultaneously in a floorplanning context due to the physical constraints involved in the design process. This leads to a floorplanning problem formulation that is very different from the traditional floorplanning for ASIC-style design.In this paper, we define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Application of the proposed algorithm to a few benchmark and industrial examples is demonstrated using a prototype tool. Results show power savings of 14%--28%, depending on the constraints imposed on the number of voltage islands and other physical-level parameters.