Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Buffered Routing Tree Construction Under Buffer Placement Blockages
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Making fast buffer insertion even faster via approximation techniques
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the need of low power methodology in VLSI and SoC designs, voltage island architecture is attracting attentions in design community. However, the corresponding EDA tools development for voltage-island-aware buffered routing is still very few. Recent related studies focused on applying dual Vdd buffers in routing tree construction, however it cannot be applied on a design using voltage island architecture due to the restriction on the ordering of low and high Vdd buffers and the lack of level converter consideration. This paper presents approaches to solving the buffer insertion and level converter assignment problem in the presence of voltage island in a low-power design, especially under the fixed buffer locations. We have implemented and modified one state-of-the-art graph-based approach for this specific routing problem and applied our efficient heuristics (one of themis based on the selection of Steiner points) to further improve the performance, considering the assignment of buffers and level converters/shifters simultaneously. The experimental results show that we can obtain massive speedup over modified prior approach, and even with lower power and delay. Furthermore, as the number of sinks increases, our approach can effectively find feasible solutions, while modified prior approach cannot find solutions within a reasonable runtime