Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat
Proceedings of the 2004 international symposium on Physical design
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Buffer insertion with adaptive blockage avoidance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 42nd annual Design Automation Conference
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fast dual-vdd buffering based on interconnect prediction and sampling
Proceedings of the 2007 international workshop on System level interconnect prediction
Information theoretic approach to address delay and reliability in long on-chip interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-scenario buffer insertion in multi-core processor designs
Proceedings of the 2008 international symposium on Physical design
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Proceedings of the 2008 international symposium on Physical design
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
Data handling limits of on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra-fast interconnect driven cell cloning for minimizing critical path delay
Proceedings of the 19th international symposium on Physical design
Shedding physical synthesis area bloat
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing electrical violations. Consequently, buffer insertion is needed on tens of thousands of nets during physical synthesis optimization. Even the fast implementation of van Ginneken's algorithm requires several hours to perform this task. This work seeks to speed up the van Ginneken style algorithms by an order of magnitude while achieving similar results. To this end, we present three approximation techniques in order to speed up the algorithm: (1) aggressive pre-buffer slack pruning, (2) squeeze pruning, and (3) library lookup. Experimental results from industrial designs show that using these techniques together yields solutions in 9 to 25 times faster than van Ginneken style algorithms, while only sacrificing less than 3% delay penalty.