Buffer insertion with accurate gate and interconnect delay computation

Is wire tapering worthwhile?

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Meeting delay constraints in DSM by minimal repeater insertion

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Designing closer to the edge (tutorial)

DATE '00 Proceedings of the conference on Design, automation and test in Europe

A graph based algorithm for optimal buffer insertion under accurate delay models

Proceedings of the conference on Design, automation and test in Europe

Buffered Steiner trees for difficult instances

Proceedings of the 2001 international symposium on Physical design

Modeling and forecasting of manufacturing variations (embedded tutorial)

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Memory-efficient interconnect optimization

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

A fast and accurate delay estimation method for buffered interconnects

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Functional correlation analysis in crosstalk induced critical paths identification

Proceedings of the 38th annual Design Automation Conference

Buffer insertion with adaptive blockage avoidance

Proceedings of the 2002 international symposium on Physical design

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Proceedings of the 2002 international symposium on Physical design

Technology-based transformations

Logic Synthesis and Verification

Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

Analog Integrated Circuits and Signal Processing

Hurwitz stable reduced order modeling for RLC interconnect trees

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Shielding effect of on-chip interconnect inductance

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Concurrent flip-flop and repeater insertion for high performance integrated circuits

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Layout-driven Timing Optimization by Generalized De Morgan Transform

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Buffer Library Selection

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Design for Variability in DSM Technologies

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

A fast algorithm for identifying good buffer insertion candidate locations

Proceedings of the 2004 international symposium on Physical design

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Path based buffer insertion

Proceedings of the 42nd annual Design Automation Conference

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Proceedings of the 42nd annual Design Automation Conference

RITC: Repeater Insertion with Timing Target Compensation

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design

Improving run times by pruned application of synthesis transforms

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design

Variability-Driven Buffer Insertion Considering Correlations

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Making fast buffer insertion even faster via approximation techniques

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Low-power repeater insertion with both delay and slew rate constraints

Proceedings of the 43rd annual Design Automation Conference

Fast algorithms for slew constrained minimum cost buffering

Proceedings of the 43rd annual Design Automation Conference

Repeater insertion for concurrent setup and hold time violations with power-delay trade-off

Proceedings of the 2007 international symposium on Physical design

A new RLC buffer insertion algorithm

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Multi-scenario buffer insertion in multi-core processor designs

Proceedings of the 2008 international symposium on Physical design

Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations

Proceedings of the 2008 international symposium on Physical design

Fast interconnect synthesis with layer assignment

Proceedings of the 2008 international symposium on Physical design

A practical repeater insertion flow

Proceedings of the 18th ACM Great Lakes symposium on VLSI

On the decreasing significance of large standard cells in technology mapping

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs

Proceedings of the 2009 International Conference on Computer-Aided Design

An efficient phase detector connection structure for the skew synchronization system

Proceedings of the 47th Design Automation Conference

Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools

Microelectronics Journal

An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Shedding physical synthesis area bloat

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem

Proceedings of the 50th Annual Design Automation Conference