Fully coupled dynamic electro-thermal simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electro-thermal and logi-thermal simulation of VLSI designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
Timing Minimization by Statistical Timing hMetis-based Partitioning
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Placement Method Targeting Predictability Robustness and Performance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The care and feeding of your statistical static timer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variability inspired implementation selection problem
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Analysis of Process Variation's Effect on SRAM's Read Stability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Statistical framework for technology-model-product co-design and convergence
Proceedings of the 44th annual Design Automation Conference
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Protection of Sensitive Security Parameters in Integrated Circuits
Mathematical Methods in Computer Science
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power analysis attacks: a novel class of attacks to nanometer cryptographic circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Extracting device fingerprints from flash memory by exploiting physical variations
TRUST'11 Proceedings of the 4th international conference on Trust and trustworthy computing
Tolerating process variations in nanophotonic on-chip networks
Proceedings of the 39th Annual International Symposium on Computer Architecture
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reliability challenges for electric vehicles: from devices to architecture and systems software
Proceedings of the 50th Annual Design Automation Conference
AppAdapt: opportunistic application adaptation in presence of hardware variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Process-induced variations are an important consideration in the design of integrated circuits. Until recently, it was sufficient to model die-to-die shifts in device performance, leading to the well known worst-case modeling and design methodology [1, 2]. However, current and near-future in-tegrated circuits are large enough that device and intercon-nect parameter variations within the chip are as important as those same variations from chip to chip. This presents a new set of challenges for process modeling and characterization and for the associated design tools and method-ologies. This paper examines the sources and trends of process variability, the new challenges associated with the increase in within-die variability analysis, and proposes a modeling and simulation methodology to deal with this variability.