Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Potential-NRG: placement with incomplete data
DAC '98 Proceedings of the 35th annual Design Automation Conference
Measurement techniques and interconnect estimation
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling and forecasting of manufacturing variations (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Creating and exploiting flexibility in steiner trees
Proceedings of the 38th annual Design Automation Conference
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Predictability: definition, ananlysis and optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Nostradamus: a floorplanner of uncertain designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A temperature-aware simulation environment for reliable ULSI chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We study the relationship between robustness,predictability andperformance of VLSI circuits. It is shown that predictability andperformance are conflicting objectives. Performance and robustnessare statically conflicting objectives but they are statistically non-conflicting.We propose and develop means for changing a standard timing-driven partitioning-based placement algorithm in order to design more predictable and robust circuits without sacrificingmuch of performance.