Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Timing Minimization by Statistical Timing hMetis-based Partitioning
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Placement Method Targeting Predictability Robustness and Performance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Interconnect lifetime prediction under dynamic stress for reliability-aware design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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In this paper, we present a temperature-aware simulation environment, iTAS, which has been developed for the design of thermally reliable ultra-large scale integrated (ULSI) chips. This environment provides advisory information from the early chip design phase to the post-layout analysis phase. Several important applications, including temperature-sensitive timing analysis, efficient on-chip hot-spot identification, and thermally reliable package design are addressed, iTAS can be used not only for reliability checking, but also for better thermal engineering to enhance the overall chip performance