Quadratic Boolean programming for performance-driven system partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
Statistical delay modeling in logic design and synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Measurement techniques and interconnect estimation
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Modeling and forecasting of manufacturing variations (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Global clustering-based performance-driven circuit partitioning
Proceedings of the 2002 international symposium on Physical design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A matrix synthesis approach to thermal placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A temperature-aware simulation environment for reliable ULSI chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we present statistical timing driven hMetis-basedpartitioning. We approach timing drivenpartitioning from a different perspective: we use thestatistical timing criticality concept to change thepartitioning process itself. We exploit the hyperedgecoarsening scheme of the hMetis partitioner for ourtiming minimization purpose. This allows us to performpartitioning such that the most critical nets in the circuitare not cut and therefore timing minimization can beachieved. The use of the hMetis partitioning algorithmmakes our partitioning methodology fast. Simulationsresults show that 22% average delay improvement can beobtained. Furthermore, as a result of using the statisticaltiming model, the partitioning results can toleratechanges in temperature and process variation, hencecausing less delay change compared to partitioning usingstatic timing models.