Global clustering-based performance-driven circuit partitioning

Authors:
Jason Cong;Chang Wu
Affiliations:
University of California at Los Angeles, Los Angeles, CA;Aplus Design Technologies, Inc., Los Angeles, CA
Venue:
Proceedings of the 2002 international symposium on Physical design
Year:
2002

Citing 8
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Abstract

In this paper, we propose a new global clustering based multi-level partitioning algorithm for performance optimization. Our algorithm computes a delay minimal K-way partition first, then gradually reduces the cutsize while keeping the circuit delay by de-clustering and refinement. Our test results on a set of MCNC sequential examples show that we can reduce the delay by 30%, while increasing the cutsize by 28% on average, when compared with hMetis [5]. Our algorithm consistently outperforms state-of-the-art partitioning algorithms [2, 5, 3] on circuit delay with reasonable cost on the cutsize.