Timing optimization for multi-level combinational networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A fast and effective heuristic for the feedback arc set problem
Information Processing Letters
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Speeding up technology-independent timing optimization by network partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A fast algorithm for finding dominators in a flowgraph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Global clustering-based performance-driven circuit partitioning
Proceedings of the 2002 international symposium on Physical design
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Treegion Scheduling for Wide Issue Processors
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimum clustering for delay minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit clustering for delay minimization under area and pin constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design hierarchy-guided multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven logic bi-decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel circuit clustering for delay minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable for logic restructuring. As a result, a scalable and efficient strategy for delay optimization is proposed and evaluated, showing tangible improvements with respect to existing techniques. A comparison with a standard mincut-based partitioning technique is also presented.