Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Performance-optimal clustering with retiming for sequential circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Performance-driven multi-level clustering with application to hierarchical FPGA mapping
Proceedings of the 38th annual Design Automation Conference
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On minimum delay clustering without replication
Integration, the VLSI Journal
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Integration, the VLSI Journal
Performance-driven multi-level clustering for combinational circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Dominator-based partitioning for delay optimization
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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We consider the problem of circuit partitioning for multiple-chip implementations. One motivation for studying this problem is the current need for good partitioning tools for implementing a circuit on multiple field programmable gate array (FPGA) chips. We allow duplication of logic gates as it could be used to reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the nonoptimality occurs, and we show that the condition rarely occurs in practice. We tested our algorithm on a set of benchmark circuits, and consistently obtained optimal or near-optimal delays