Optimal clustering for delay minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
On circuit clustering for area/delay tradeoff under capacity and pin constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Circuit clustering for delay minimization under area and pin constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-optimal clustering targeting low-power VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we show that the problem of clustering a combinational circuit under the area or pin constraint so that the clusters are disjoint and the overall input/output delay is minimized is computationally intractable. The minimization of the delay with the disjoint cluster requirement was up to now an open problem, whereas the version that allows replicated components in the clusters is known to have a fast polynomial-time solution. We also describe an improved heuristic for the problem and give comparative experimental results that illustrate the tradeoff between the general decrease in the number of clusters and the general increase in the overall delay of the disjoint over the non-disjoint version.