Performance-driven multi-level clustering for combinational circuits

Authors:
C. N. Sze;Ting-Chi Wang
Affiliations:
Texas A&M University, College Station, Texas;National Tsing Hua University, Hsinchu, Taiwan
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

Citing 3
Cited 0

Performance-driven multi-level clustering with application to hierarchical FPGA mapping

Proceedings of the 38th annual Design Automation Conference
Optimum clustering for delay minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit clustering for delay minimization under area and pin constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

In this paper, an effective algorithm is presented for performance driven multi-level clustering for combinational circuits, and is applicable to hierarchical FPGAs. With a novel graph contraction technique, which allows some crucial delay information of a lower-level clustering to be maintained in the contracted graph, our algorithm recursively divides the lower-level clustering into the next higher-level one in a way that each recursive clustering step is accomplished by applying a modified single-level circuit clustering algorithm based on [1]. We test our algorithm on the two-level clustering problem and compare it with the latest algorithm in [2]. Experimental results show that our algorithm achieves, on average, 12% more delay reduction when compared to the best results (from TLC with full node-duplication) in [2]. In fact, our algorithm is the first one for the general multi-level circuit clustering problem with more than two levels.