Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Global clustering-based performance-driven circuit partitioning
Proceedings of the 2002 international symposium on Physical design
A New Algorithm for Multi-objective Graph Partitioning
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Proceedings of the 2003 international symposium on Physical design
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Constant factor approximation of vertex-cuts in planar graphs
Proceedings of the thirty-fifth annual ACM symposium on Theory of computing
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance-driven global placement via adaptive network characterization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Timing-driven placement based on monotone cell ordering constraints
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Dominator-based partitioning for delay optimization
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
A hybrid partitioning algorithm based on natural mechanisms of decision making
Scientific and Technical Information Processing
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a new objective function that incorporates a truly path-based delay component for the most critical paths. To avoid semi-critical paths from becoming critical, the traditional slack based delay component is also included in the cost function. The proposed timing driven partitioning algorithm is built on top of the hMetis algorithm, which is very efficient. Simulations results show that 14% average delay improvement can be obtained. Smooth trade-off between cutsize and delay is possible in our algorithm.