Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Standard cell placement for even on-chip thermal distribution
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimal topology exploration for application-specific 3D architectures
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Wire congestion and thermal aware 3D global placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The impact of liquid cooling on 3D multi-core processors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Application exploration for 3-d integrated circuits: TCAM, FIFO, and FFT case studies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
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We examine the performance of custom circuits in an emerging technology known as three-dimensional integration. By combining multiple device layers with a high-density inter-layer interconnect, 3D integration of a given circuit is expected to provide better timing and energy performance relative to a single-wafer implementation of the same circuit. In this paper, we show that by using our performance-driven design tool for 3D ICs, the interconnect energy dissipation of standard-cell circuits can be reduced by 24% to 42% using two to five device layers respectively. Similarly, the interconnect energy-delay product can be reduced by 30% to 50%.At the same time, thermal performance in 3D ICs is expected to be a critical issue. By incorporating thermal management and analysis into our placement tool, we may investigate the thermal scalability of 3D integration. We find that the thermal performance actually can be improved with the use of a modest number of additional device layers. Also, we show that the absolute die temperature can be controlled through the use of extra silicon.