Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Exploring SOI device structures and interconnect architecures for 3-dimensional integration
Proceedings of the 38th annual Design Automation Conference
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multidisciplinary heat generating logic block placement optimization using genetic algorithm
Microelectronics Journal
A criticality-driven microarchitectural three dimensional (3D) floorplanner
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip thermal analysis for the early design stage via generalized integral transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
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The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce the maximum temperature and wire congestion of 3D circuits without compromising total wirelength and via count. Our approach consists of two phases. First, we use a multi-level min-cut placement with a modified gain function for local wire congestion and dynamic power consumption reduction. Second, we perform simulated annealing together with full-length thermal analysis and global routing for global wire congestion and maximum temperature reduction. Our experimental results show smooth tradeoff among congestion, temperature, wirelength, and via.