Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
The need for a full-chip and package thermal model for thermally optimized IC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Wire congestion and thermal aware 3D global placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Journal of Intelligent Manufacturing
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A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5^oC, compared to the case in which only the wiring length is minimized.