Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
IBM Journal of Research and Development
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect lifetime prediction under dynamic stress for reliability-aware design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Coupled power and thermal simulation with active cooling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
EDA challenges facing future microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Proceedings of the 2006 international symposium on Low power electronics and design
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient power modeling and software thermal sensing for runtime temperature monitoring
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Thermal-aware task scheduling at the system software level
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Multidisciplinary heat generating logic block placement optimization using genetic algorithm
Microelectronics Journal
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic thermal management using thin-film thermoelectric cooling
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Thermal analysis and modeling of embedded processors
Computers and Electrical Engineering
Parameterized architecture-level dynamic thermal models for multicore microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance-aware thermal management via task scheduling
ACM Transactions on Architecture and Code Optimization (TACO)
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
Compact thermal modeling for packaged microprocessor design with practical power maps
Integration, the VLSI Journal
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Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally self-consistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip- and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view