Thermal-aware methodology for repeater insertion in low-power VLSI circuits

Authors:
Ja Chun Ku;Yehea Ismail
Affiliations:
Northwestern University;Northwestern University
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

Citing 10
Cited 1

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Abstract

In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90nm and 65nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks.