Modeling microprocessor performance
Modeling microprocessor performance
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A compact physical via blockage model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A detailed cost model for concurrent use with hardware/software co-design
Proceedings of the 39th annual Design Automation Conference
Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices
Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
IEEE Transactions on Computers
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Scaling of Temperature-Dependent Effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning
Proceedings of the International Conference on Computer-Aided Design
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Proceedings of the International Conference on Computer-Aided Design
Cost evaluation on reuse of generic network service dies in three-dimensional integrated circuits
Microelectronics Journal
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Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to alternatives such as tiled silicon and single-level embedded modules as well as 3-D die stacks. Among the various choices, finding an optimal solution for system implementation deals usually with cost, performance, power, thermal, and technological tradeoff analyses at the system conceptual level. It has been estimated that decisions made in the first 20% of the design cycle influence up to 80% of the final product cost. In this paper, we discuss realistic metrics appropriate for performance and cost tradeoff analyses both at the system conceptual level in the early stages of the design cycle and in the implementation phase, for verification. In order to validate the proposed metrics and methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and the performance tradeoffs discussed. This case study is used to highlight the importance of a cost and performance tradeoff analysis early in the design flow.