Modeling the Economics of Testing: A DFT Perspective
IEEE Design & Test
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An efficient approach to sip design integration
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Testing Circuit-Partitioned 3D IC Designs
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Pre-bond testable low-power clock tree design for 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
Applications driving 3D integration and corresponding manufacturing challenges
Proceedings of the 48th Design Automation Conference
System-level design space exploration for three-dimensional (3D) SoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Future memory and interconnect technologies
Proceedings of the Conference on Design, Automation and Test in Europe
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Hi-index | 0.00 |
Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However, when deciding to adopt this emerging technology as a mainstream design approach, designers must consider the cost of 3D integration. IC testing is a key factor that affects the final product cost, and it could be a major portion of the total IC cost. In 3D IC design, various testing strategies and different integration methods could affect the final product cost dramatically, and the interaction with other cost factors could result in various trade-offs. This paper develops a comprehensive and parameterized testing cost model for 3D IC integration, and analyzes the trade-offs associated with testing strategies and testing circuit overheads. With the proposed testing cost model, designers can explore the most cost-effective integration and testing strategies for 3D IC chips.