Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect level prediction for I_DDQ testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Characterization and analysis of errors in circuit test
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tackling Test Trade-offs from Design, Manufacturing to Market using Economic Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A New Test/Diagnosis/Rework Model for Use in Technical Cost Modeling of Electronic Systems Assembly
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ASIC Manufacturing Test Cost Prediction at Early Design Stage
ITC '97 Proceedings of the 1997 IEEE International Test Conference
BOARD LEVEL AUTOMATED FAULT INJECTION FOR FAULT COVERAGE AND DIAGNOSTIC EFFICIENCY
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Quality of Electronic Design: From Architectural Level to Test Coverage
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Design for Testability: It is time to deliver it for Time-to-Market
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Exploiting Defect Clustering to Screen Bare Die for Infant Mortality Failures: An Experimental Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Physically-aware N-detect test pattern selection
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Adaptive test elimination for analog/RF circuits
Proceedings of the 46th Annual Design Automation Conference
Back annotation of physical defects into gate-level, realistic faults in digital ICs
ITC'94 Proceedings of the 1994 international conference on Test
The effect on quality of non-uniform fault coverage and fault probability
ITC'94 Proceedings of the 1994 international conference on Test
Manufacturing test simulator: a concurrent engineering tool for boards and MCMs
ITC'94 Proceedings of the 1994 international conference on Test
IC quality and test transparency
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Sufficient testing in a self-testing environment
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Analog test metrics estimates with PPM accuracy
Proceedings of the International Conference on Computer-Aided Design
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Proceedings of the International Conference on Computer-Aided Design
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®
Journal of Electronic Testing: Theory and Applications
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
| Hi-index | 14.98 |
This correspondence presents a single equation relating the defect level of LSI chips to the yield and stuck-at-fault coverage with some assumptions. It is assumed that the faults occur randomly on the chips, which implies no clustering. This concept is extended to modules on boards.