Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A methodology for testability enhancement at layout level
Journal of Electronic Testing: Theory and Applications
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
Stuck Fault and Current Testing Comparison Using CMOS Chip Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Physical DFT for High Coverage of Realistic Faults
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
ITC '98 Proceedings of the 1998 IEEE International Test Conference
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IC complexity moves the design activity upwards, into higher levels of abstraction. Product quality requires the move of test activity downwards, down to IC physical level. High quality test requires the ability to cover physical defects. However, circuit complexity makes test preparation, at transistor level, prohibitive. A methodology for back annotation of physical defects into gate level realistic faults, is proposed in this paper. Bridging faults are selected, as they are the most likely faults in present-day process lines. It is shown that realistic faults, associated with routing patterns, can be used to represent the overall fault set, leading to an accurate evaluation of the Defect Level, used as the test quality indicator. A method to generate gate-level, realistic fault lists from the IC layout is presented, and is validated by simulation results.