On applying non-classical defect models to automated diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new method for testing mixed analog and digital circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Tolerance DC bands of CMOS operational amplifier
ATS '95 Proceedings of the 4th Asian Test Symposium
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Hierarchical Defect-Oriented Fault Simulation for Digital Circuits
ETW '00 Proceedings of the IEEE European Test Workshop
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Fault Models and Test Strategies for a Two-Bit per Cell DRAM
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Highly testable and compact single output comparator
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Modular TSC Checkers for Bose-Lin and Bose Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Digital Signature Proposal for Mixed-Signal Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPU
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Bridging Fault Diagnosis in the Absence of Physical Information
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On-Line Testing Scheme for Clock's Faults
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quality of Electronic Design: From Architectural Level to Test Coverage
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Reducing Embedded SRAM Test Time under Redundancy Constraints
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Automated failure population creation for validating integrated circuit diagnosis methods
Proceedings of the 46th Annual Design Automation Conference
Defect-based test optimization for analog/RF circuits for near-zero DPPM applications
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
QTAG: a standard for test fixture based IDDQ/ISSQ monitors
ITC'94 Proceedings of the 1994 international conference on Test
Development of a class 1 QTAG monitor
ITC'94 Proceedings of the 1994 international conference on Test
Testing CMOS logic gates for realistic shorts
ITC'94 Proceedings of the 1994 international conference on Test
Residual charge on the faulty floating gate MOS transistor
ITC'94 Proceedings of the 1994 international conference on Test
Variable supply voltage testing for analogue CMOS and bipolar circuits
ITC'94 Proceedings of the 1994 international conference on Test
Analogue fault simulation based on layout dependent fault models
ITC'94 Proceedings of the 1994 international conference on Test
Back annotation of physical defects into gate-level, realistic faults in digital ICs
ITC'94 Proceedings of the 1994 international conference on Test
Fault modeling and test algorithm development for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A BIST design of structured arrays with fault-tolerant layout
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
DC_IATP- an iterative analog circuit test generation program for generating DC single pattern tests
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integratedcircuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statisticaldata from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classificationof faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault modeland a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics.The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some veryinteresting observations regarding nonclassical faults.