Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
Quality Testing Requires Quality Thinking
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
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A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher-level simulation, we use the functional fault model; at the lower level, we use the defect/fault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-open's and stuck-on's. It has been shown that in the worst case a test with 100% stuck-at fault coverage may have only 50% coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results.