Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Putting the Squeeze on Test Sequences
Proceedings of the IEEE International Test Conference
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential circuit test generation using decision diagram models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting Behavioral Information in Gate-Level ATPG
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A VHDL error simulator for functional test generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Hierarchical Defect-Oriented Fault Simulation for Digital Circuits
ETW '00 Proceedings of the IEEE European Test Workshop
RT-level TPG Exploiting High-Level Synthesis Information
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
AMLETO: A Multi-language Environment for Functional Test Generation
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A Method Enabling Feasible Conformance Test Sequence Generation for EFSM Models
IEEE Transactions on Computers
High-level test generation for hardware testing and software validation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach.