Logic testing and design for testability
Logic testing and design for testability
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Speed up of behavioral A.T.P.G. using a heuristic criterion
DAC '93 Proceedings of the 30th international Design Automation Conference
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Sequential circuit test generation using decision diagram models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Functional fault modeling and simulation for VLSI devices
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
Test Synthesis with Alternative Graphs
IEEE Design & Test
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Quality Testing Requires Quality Thinking
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
How many decomposition types do we need? [decision diagrams]
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Improving topological ATPG with symbolic techniques
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
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A new hierarchical approach to test generation for digital systems is proposed. Three levels of modeling are exploited: high-level Decision Diagrams (DD) for module test planning and system constraints generating, low-level Boolean differential equations for fault constraints generating, and medium-level Binary DDs for local test pattern generation for modules under the derived set of constraints. The proposed method of generating fault constraints the first time allows to handle faults which increase the number of states in sequential circuits.Combining the high-level efficiency of solving complex deterministic search problems and medium-level accuracy of fault "transportation" analysis with low-level exact fault activation allows to reach high efficiency in test generation, and high test quality on the other hand. Experimental results compared to the known test generators are provided for demonstrating the high efficiency of test generation achieved by the proposed approach.