Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
How to Avoid Random Walks in Hierarchical Test Path Identification
ETW '00 Proceedings of the IEEE European Test Workshop
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DPDAT: DATA PATH DIRECT ACCESS TESTING
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
Testability analysis based on the identification of testable blocks with predefined properties
Microprocessors & Microsystems
Configuring flip-flops to BIST registers
ITC'94 Proceedings of the 1994 international conference on Test
Expert system for the functional test program generation of digital electronic circuit boards
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Concurrent control of multiple BIT structures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A knowledge representation scheme for DFT
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An expert test program generation system for per-pin testers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Threading of multiple scan paths in a VLSI circuit
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A New Design-for-Testability Method Based on Thru-Testability
Journal of Electronic Testing: Theory and Applications
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The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designingmore easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What hasnot evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This articledescribes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodologyincorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodologyprovides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individualprocessing is described and a new concept?I-path?is used to transfer data from one place in the circult to another. Rulesfor applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are alsopresented. Finally, a case study using a prototype system is described.