Threading of multiple scan paths in a VLSI circuit

  • Authors:
  • S. Bhawmick;M. S. Khaira;P. P. Mishra;A. Das;A. Dasgupta;P. Palchaudhury

  • Affiliations:
  • Dept. of Computer Sc. and Engg., Indian Institute of Technology, Kharagpur, India;Dept. of Computer Sc. and Engg., Indian Institute of Technology, Kharagpur, India;Dept. of Computer Sc. and Engg., Indian Institute of Technology, Kharagpur, India;Dept. of Computer Sc. and Engg., Indian Institute of Technology, Kharagpur, India;Dept. of Computer Sc. and Engg., Indian Institute of Technology, Kharagpur, India;Dept. of Computer Sc. and Engg., Indian Institute of Technology, Kharagpur, India

  • Venue:
  • ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
  • Year:
  • 1988

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Abstract

Testing of a VLSI circuit through multiple scan paths achieves concurrency in testing and reduces overall test time. This paper addresses the problem of configuring multiple scan paths in a VLSI circuit. Based on the analysis of the circuit, certain specific subcircuits are identified and a scan path is next configured for testing each such subcircuit. Rather than the algorithmic approach, a Knowledge Based System(KBS) strategy has been adopted in order to automate the approach taken by a human designer to tackle the problem.