Design for testability — a review of advanced methods
Microprocessors & Microsystems
DFTEXPERT: an expert system for design of testable VLSI circuits
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1
Design of Testable VLSI Circuits with Minimum Area Overhead
IEEE Transactions on Computers
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
An integrated cad system for design of testable vlsi circuits
An integrated cad system for design of testable vlsi circuits
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
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Testing of a VLSI circuit through multiple scan paths achieves concurrency in testing and reduces overall test time. This paper addresses the problem of configuring multiple scan paths in a VLSI circuit. Based on the analysis of the circuit, certain specific subcircuits are identified and a scan path is next configured for testing each such subcircuit. Rather than the algorithmic approach, a Knowledge Based System(KBS) strategy has been adopted in order to automate the approach taken by a human designer to tackle the problem.