Exclusive simulation of activity in digital networks
Communications of the ACM
A new heuristic test generation algorithm for sequential circuits
DAC '74 Proceedings of the 11th Design Automation Workshop
A logic design structure for LSI testability
25 years of DAC Papers on Twenty-five years of electronic design automation
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Load Balancing in a Hybrid ATPG Environment
IEEE Transactions on Computers
DAC '94 Proceedings of the 31st annual Design Automation Conference
IEEE Design & Test
Testing Defects in Scan Chains
IEEE Design & Test
IEEE Design & Test
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Automatic test generation for large digital circuits
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage
DAC '82 Proceedings of the 19th Design Automation Conference
Behavioral-level test development
DAC '79 Proceedings of the 16th Design Automation Conference
A practical approach to instruction-based test generation for functional modules of VLSI processors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Design for Testability: It is time to deliver it for Time-to-Market
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Scan Latch Design for Test Applications
Journal of Electronic Testing: Theory and Applications
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Design for Testability A Survey
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
Threading of multiple scan paths in a VLSI circuit
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
LSI logic testing: an overview
IEEE Transactions on Computers
| Hi-index | 0.01 |
With the advent of large scale and medium scale integrated circuit, test and diagnosis of digital logic circuits become more and more difficult to get an efficient and economical goal. In this paper, Test Generation Systems for testing digital logic circuits (IC Cards) in Japan are introduced. One implemented in Nippon Electric Co. is described in detail. Future problems of Test Generation Systems are also briefly discussed.