An enhancement of lssd to reduce test pattern generation effort and increase fault coverage

Authors:
Kewal K. Saluja
Affiliations:
-
Venue:
DAC '82 Proceedings of the 19th Design Automation Conference
Year:
1982

Citing 3
Cited 1

Test generation systems in Japan

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A logic design structure for LSI testability

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Automatic checking of logic design structures For compliance with testability ground rules

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Improved launch for higher TDF coverage with fewer test patterns

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

In this paper we propose designs of latches which can be used in Level Sensitive Scan Design (LSSD). These new designs can use the existing software support for design rule checks but result into a reduction of effort in test pattern generation and provide a better fault coverage. The system performance is not degraded with the use of latches proposed in this paper.