Hybrid design for testability combining scan and clock line control and method for test generation

Authors:
Sanghyeon Baeg;William A. Rogers
Affiliations:
The University of Texas at Austin, Computer Engineering Research Center, Austin, Texas;The University of Texas at Austin, Computer Engineering Research Center, Austin, Texas
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.