Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
FreezeFrame: compact test generation using a frozen clock strategy
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Random pattern testing for sequential circuits revisited
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Hybrid design for testability combining scan and clock line control and method for test generation
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 0.00 |