A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Design and synthesis for testability using architectural descriptions
Design and synthesis for testability using architectural descriptions
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Novel Approach to Random Pattern Testing of Sequential Circuits
IEEE Transactions on Computers
FreezeFrame: compact test generation using a frozen clock strategy
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Partial Set for Flip-Flops Based on State Requirement for Non-Scan BIST Scheme
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Increasing testability by clock transformation (getting rid of those darn states)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A genetic algorithm framework for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a new approach to Built-in Self-Test (BIST) for logic circuits that achieves comparable fault coverages to Scan BIST with less hardware overhead and no impact on performance. We combine clock partitioning to create independent clocks with a selectivefreezing of clock signals to form various pipeline configurations during testing. Since no scan operations are performed, tests can be applied at the operational speed of the circuit. Experimental results are presented for several benchmark circuits to demonstrate the effectiveness of the approach.