A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A testability metric for path delay faults and its application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Fast test application technique without fast scan clocks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Efficient scan-based BIST scheme for low power testing of VLSI chips
Proceedings of the 2006 international symposium on Low power electronics and design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper illustrates that for existing scan-based Built-InSelf-Test (BIST) architectures under the pseudo-randomtesting scheme, scanning all flip-flops may not be the beststrategy for achieving high fault coverage with a practicallimit on test length. In general, for scan-based BIST, notscanning flip-flops with relatively high pseudo-random observabilitiesthrough the primary outputs may indeed improvethe fault coverage as well as the test application time.We illustrate the issues and present a flip-flop selection strategyfor scan-based BIST to maximize the fault coverageand reduce the test application time. Experiments havebeen conducted based on an industrial tool psb2 for severalbenchmark circuits. The results show that the almost-full-scancircuits based on our flip-flop selection strategy canachieve higher fault coverages and significantly shorter testapplication time as compared with the full-scan circuits.