Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
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Built-in self-test (BIST) schemes need to set the state of the circuit under test (CUT) for each test vector applied. The two primary techniques by which the state is set are test-per-scan and test-per-clock. In a test-per-scan scheme, circuit states are set using one or more scan chains. Several scan cycles are required to apply a single test vector. In very large circuits, the time to apply each test vector may be quite high. The direct option of reducing test time with a fast scan clock is difficult to realize in practice. In a test-per-clock scheme, all circuit flip-flops are loaded in parallel. A new test vector can be applied in each cycle. The area overhead incurred in accessing each storage element directly is quite significant. We propose a new Broadcast BIST (B2IST) scheme as a compromise between the two approaches. B2IST uses time-division multiplexing (TDM) to load multiple storage elements in a broadcast group in a single clock cycle, but through only a single scan data input. Based on our B2IST simulation, we compare the layout overhead and performance of B2IST with that of traditional BIST schemes on ISCAS benchmark circuits. Thus, B2IST can achieve the performance of a test-per-clock scheme, but only incur the overhead of a test-per-scan scheme.