Integration of partial scan and built-in self-test

Improving the test quality for scan-based BIST using a general test application scheme

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Journal of Electronic Testing: Theory and Applications

Embedded software-based self-testing for SoC design

Proceedings of the 39th annual Design Automation Conference

Fast test application technique without fast scan clocks

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

A Unified DFT Approach for BIST and External Test

Journal of Electronic Testing: Theory and Applications

A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing

Journal of Electronic Testing: Theory and Applications

Functionally Testable Path Delay Faults on a Microprocessor

IEEE Design & Test

An almost full-scan BIST solution-higher fault coverage and shorter test application time

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Impact of Partial Reset on Fault Independent Testing and BIST

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Test Program Synthesis for Path Delay Faults in Microprocessor Cores

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Efficient Test Mode Selection & Insertion for RTL-BIST

ITC '00 Proceedings of the 2000 IEEE International Test Conference

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability