Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Journal of Electronic Testing: Theory and Applications
Automated BIST for Sequential Logic Synthesis
IEEE Design & Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Parity-Scan Design to Reduce the Cost of Test Application
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper introduces a new multi-mode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the need of any design changes. As in the case of scan, the new element is used in place of regular flip-flops in the design library. Interconnect overhead is comparable to scan with reset. Concurrent with normal operation, the design accumulates a signature of the state variables in the scan-register configured as a multiple input signature analyzer. Thus virtually complete state observability is achieved without the need of scanning-out the state for each test-input. The pseudorandom states of the MISA can also be utilized as state inputs in circular testing. In this way, most faults are covered in a pseudorandom, "test per clock" mode. Only a few random pattern resistant faults require scan, greatly reducing test application time. Pseudorandom delay testing of the true normally active circuit paths is also possible. Two-pattern tests are supported. Finally, we show that the new memory element can also be used for fault-tolerant design.