Circular self-test path: a low-cost BIST technique
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Behavioral Model Synthesis with Cones
IEEE Design & Test
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Circular Self-Test Path for FSMs
IEEE Design & Test
Random pattern testability of memory control logic
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
14.2 Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
IEEE Design & Test
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An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone.