Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Automated BIST for Sequential Logic Synthesis
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Structural constraints for circular self-test paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Comments on “Test efficiency analysis of random self-test of sequential circuits”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evolving effective CA/CSTP: BIST architectures for sequential circuits
Proceedings of the 2001 ACM symposium on Applied computing
DFT and BIST of a Multichip Module for High-Energy Physics Experiments
IEEE Design & Test
CA-CSTP: A New BIST Architecture for Sequential Circuits
ETW '00 Proceedings of the IEEE European Test Workshop
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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The Circular Self-Test Path (CSTP) technique is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The first goal of this article is to assess the effectiveness of this technique from an experimental point of view; the CSTP version of several circuits from the ISCAS'89 benchmark set, as well as of a set of industrial circuits, has been built, and the attainable fault coverage has been evaluated through fault simulation experiments.The results show that in many cases a very high fault coverage is attained with a limited number of clock cycles; in other cases the fault coverage remains very low no matter the length of the test session. This is due to the circuit entering a loop, which often happens with small and medium FSMs or when short chains must be used. This danger cannot be avoided even if clever strategies for ordering the flip-flops are adopted to reduce the functional adjacency among the cells of the chain.The second goal of the article is therefore to state that the test length before a cycle in the State Transition Graph is entered can be increased and fault coverage improved by carefully choosing the initial state. Eventually, the article presents an approach based on binary decision diagrams and symbolic traversal Techniques to solve the problem. The approach is particularly suited for FSMs deriving from synthesized control parts, and it is being integrated into an industrial design flow supporting testable synthesis.