Logic testing and design for testability
Logic testing and design for testability
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Journal of Electronic Testing: Theory and Applications
Automated BIST for Sequential Logic Synthesis
IEEE Design & Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
Parity-Scan Design to Reduce the Cost of Test Application
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A BIST Structure to Test Delay Faults in a Scan Environment
ATS '98 Proceedings of the 7th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Multimode scan: Test per clock BIST for IP cores
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
This paper introduces a new multi-mode scannable memory element whichallows pseudorandom testing to be integrated with scan in sequentialcircuits without the need of any design changes. As in the case ofscan, the new element is used in place of regular flip-flops in thedesign library. Concurrent with normal operation, the design canaccumulate a signature of the state variables in the scan-registerconfigured as a multiple input signature analyzer (MISA). Thusvirtually complete state observability is achieved without the need ofscanning-out the state for each test-input. The pseudorandom states ofthe MISA can also be utilized as state inputs in pseudorandom testing.In this way, most faults are covered in a pseudorandom, “test perclock” mode. Only a few random pattern resistant faults require scan,greatly reducing test application time. Pseudorandom delay testing ofthe true normally active circuit paths is also possible. Two-patterntests are supported. Finally, we show that the new memory element canalso be used for fault-tolerant design.