Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Simplifying Sequential Circuit Test Generation
IEEE Design & Test
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Checking Combinational Circuits by the Method of Logic Complement
Automation and Remote Control
Checking of combinational circuits basing on modification sum codes
Automation and Remote Control
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
A test clock reduction method for scan-designed circuits
ITC'94 Proceedings of the 1994 international conference on Test
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