On-Line Error Detection for Bit-Serial Multipliers in GF(2m)

Authors:
Sebastian Fenn;Michael Gossel;Mohammed Benaissa;David Taylor
Affiliations:
Department of Electronic and Electrical Engineering, The University of Huddersfield, Queensgate, Huddersfield, West Yorkshire, HD1 3DH, UK. E-mail: S.T.J.Fenn@hud.ac.uk;Fault Tolerant Computing Group, The University of Potsdam, PSF 601553, 14415 Potsdam, Germany. E-mail: mgoessel@mpag-inf.uni-potsdam.de;Department of Electronic and Electrical Engineering, The University of Huddersfield, Queensgate, Huddersfield, West Yorkshire, HD1 3DH, UK. E-mail: M.Benaissa@hud.ac.uk;Department of Electronic and Electrical Engineering, The University of Huddersfield, Queensgate, Huddersfield, West Yorkshire, HD1 3DH, UK. E-mail: D.Taylor@hud.ac.uk
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
1998

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Abstract

In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-lineerror detection can be incorporated into these multipliers with very lowhardware overheads. These hardware overheads are generally independent of m and comprise only a handful of gates, so for large values of m theseoverheads are particularly low. The fault coverage of the presentedstructures has been investigated by simulation experiment and shown to rangebetween 90% and 94.3%.