Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)

Authors:
Chiou-Yng Lee;Che Wun Chiou;Jim-Min Lin
Affiliations:
Program Coordination Department, Chunghwa Telecommunication Laboratories, Chung-Li, Tao-Yuan, R.O.C. 320;Department of Information and Computer Science, Ching Yun University, Chung-Li, Taoyuan, R.O.C. 320;Department of Information Engineering, Feng Chia University, Taichung City, R.O.C. 407
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2005

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Abstract

The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2m) according to the Fenn's multiplier in [7]. Although, the proposed method increases the space complexity overhead about 27% and the latency overhead about one extra clock cycle as compared to Fenn's multiplier. Our analysis shows that all single stuck-at faults can be detected concurrently.